00154 Verilog 杂项

前言

介绍一些 Verilog 的杂项。

操作系统：Windows 10 专业版

参考文档

1. In all code, it’s generally a good idea to write a brief summary of the module

a brief summary of the module

源教程地址: https://www.eevblog.com/forum/fpga/commenting-verilog-code-best-practice/msg2612196/#msg2612196 .

// This module implements a 32 bit up/down counter with asynchronous reset.
//
// Inputs:
//        clock - The clock for the counter
//        direction - The direction of the counter.  High=increment, low=deincrement
//        reset - active-high reset of the counter
//
// Outputs:
//        out[31:0] - the output of the counter
//
// The counter will either increment or deincrement the counter by one on the rising edge of the clock pulse, depending on the value of direction.
// The counter will reset to zero immediately upon assertion of the reset input and will stay reset while the reset input is held high, even if a clock pulse is received.

结语

第一百五十四篇博文写完，开心！！！！

今天，也是充满希望的一天。